The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device that performs a data access operation by replacing a defective memory cell with a normal redundancy memory cell.
With rapid increase in integration density of semiconductor memory devices including double data rate (DDR) synchronous dynamic random access memory (SDRAM), tens of millions of memory cells are integrated into a single semiconductor memory device. Such memory cells constitute memory cell arrays arranged uniformly, and those groups are called a memory cell mat.
If a fail occurs in a memory cell in a semiconductor memory device, the semiconductor memory device may not normally perform a desired operation. As the fabrication technology of semiconductor memory devices has been advanced, defects occur in a very small number of memory cells. Thus, if semiconductor memory devices are discarded as defective items when defects occur in few memory cells, product yield suffers. To overcome such problems, redundancy memory cells are further provided within semiconductor memory devices, separately from normal memory cells. When defects occur in normal memory cells, those memory cells are replaced with the redundancy memory cells. Hereinafter, memory cells that must be replaced with the redundancy memory cells due to their defects will be referred to as “defective memory cells”.
Meanwhile, memory cell architectures of the semiconductor memory devices may be classified into a folded bit line architecture and an open bit line architecture.
In the case of the folded bit line architecture, an active bit line (for example, a bit line) driving data, and a reference bit line (for example, a complementary bit line) are disposed in the same memory cell mat, with respect to a bit line sense amplifier disposed in a core region of the semiconductor memory device. Thus, the same noises are reflected on the bit line and the complementary bit line, and such noises offset each other. Due to such an offset effect, the folded bit line architecture ensures a stable operation with respect to noises. On the other hand, in the case of the open bit line architecture, a bit line and a complementary bit line are disposed in different memory cell mats, with respect to a bit line sense amplifier. Thus, noise occurring in the bit line is different from noise occurring in the complementary bit line, and the open bit line architecture is vulnerable to noises.
The folded bit line architecture is designed to have an 8F2 unit memory cell structure, and the open bit line architecture is designed to have a 6F2 unit memory cell structure. Those unit memory cell structures are a factor in determining the size of the semiconductor memory device. In comparison with the same data storage capacity, the semiconductor memory device having the open bit line architecture can be designed to be smaller in size than the semiconductor memory device having the folded bit line architecture.
Meanwhile, the semiconductor memory device stores or outputs data according to commands requested by a central processing unit (CPU) or the like. When a data access operation is requested by the CPU, a word line corresponding to a row address is activated, and a signal corresponding to a column address is activated. Then, the data access operation is performed on a corresponding memory cell. Semiconductor memory devices may have a different number of word lines. However, the number of word lines typically corresponds to the number of bit lines. For example, when the number of address bits is m, the semiconductor memory device is designed to have 2m word lines (where m is a natural number). Thus, the number of word lines corresponding to a single memory cell mat may be 256, 512, and so on. In this case, the number of word lines corresponds to the umber of memory cell arrays.
In the case of the open bit line architecture, however, the number of word lines corresponding to a single memory cell mat is designed to be in a range of greater than 2n and less than 2n+1 (where n is a natural number), for example, 384 or 420, considering the operating margin of the bit line sense amplifier, noise, and design efficiency. Therefore, compared with the folded bit line architecture designed to have 2m word lines, the open bit line architecture has unused memory cell arrays, that is, dummy memory cell arrays. The dummy memory cell arrays are included in the memory cell mat, but they are designed separately from 2m. The word lines connected to the dummy memory cell arrays are commonly grounded and are unused.
FIG. 1 illustrates a memory cell array architecture of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a normal memory cell array in which a plurality of memory cells are arranged. For illustration purposes, the side above a bit line sense amplifier block 150 will be referred to as an even memory cell mat 110, and the side below the bit line sense amplifier block 150 will be referred to as an odd memory cell mat 130. The bit line sense amplifier block 150 includes a plurality of bit line sense amplifiers SA.
The even memory cell mat 110 and the odd memory cell mat 130 include a plurality of word lines WL, and a specific word line WL is activated in response to a data access operation, for example, a read or write operation. The bit line sense amplifier SA is connected to a bit line BLT and a complementary bit line BLB, and senses and amplifies a voltage difference between the bit line BLT and the complementary bit line BLB.
Another bit line sense amplifier block (not shown) performing the same function as the bit line sense amplifier block 150 is arranged above the even memory cell mat 110 and connected to the complementary bit lines BLB arranged in the even memory cell mat 110. Moreover, another bit line sense amplifier block (not shown) is arranged below the odd memory cell mat 130 and connected to the bit lines BLT arranged in the odd memory cell mat 130.
The data access operation of the semiconductor memory device illustrated in FIG. 1 will be described below.
When one word line WL is activated in the data access operation, the normal memory cell array connected to the activated word line WL is activated. That is, the normal memory cells connected to the activated word line WL are activated, and data stored in the normal memory cells are transferred to the corresponding bit lines.
If the word line WL provided in the even memory cell mat 110 is activated, data of the normal memory cells are transferred through the corresponding bit lines BLT to the bit line sense amplifier block 150. In this case, the complementary bit lines BLB provided in the odd memory cell mat 130 serve as a reference in sensing and amplifying the data transferred through the bit lines BLT. On the contrary, if the word line WL provided in the odd memory cell mat 130 is activated, data of the normal memory cells are transferred through the corresponding complementary bit lines BLB to the bit line sense amplifier block 150. In this case, the bit lines BLT provided in the even memory cell mat 110 serve as a reference in sensing and amplifying the data transferred through the complementary bit lines BLB.
FIG. 2 illustrates a dummy memory cell array and a redundancy memory cell array of a conventional semiconductor memory device.
Referring to FIG. 2, the semiconductor memory device includes a normal memory cell array 210, a dummy memory cell array 230, and a redundancy memory cell array 250. The normal memory cell array 210 and the dummy memory cell array 230 are designed within one memory cell mat, and the redundancy memory cell array 250 is designed separately from the memory cell mat. The dummy memory cell array 230 is provided separately from the address bits. A memory cell array corresponding to four dummy word lines DWL is exemplified in FIG. 2. The dummy word lines DWL of the dummy memory cell array 230 are connected to the ground terminal VSS.
The redundancy memory cell array 250 is provided for replacing defective memory cells among the normal memory cells. A memory cell array corresponding four redundancy word lines RWL is exemplified in FIG. 2. When the redundancy word lines RWL are activated, the corresponding redundancy memory cells of the redundancy memory cell array 250 are activated to transfer data through the bit lines BLT and the complementary bit lines BLB.
An operation of repairing a defective memory cell in the semiconductor memory device of FIG. 2 will be described below. For illustration purposes, it is assumed that the normal memory cell array 210 includes a defective memory cell.
When an address corresponding to a defective memory cell is applied in a data access operation, the semiconductor memory device activates a redundancy word line RWL corresponding to the address, instead of a word line WL corresponding to the address. Therefore, the data access operation corresponding to the address is performed on the redundancy memory cell included in the redundancy memory cell array 250 operating normally, instead of the defective memory cell included in the normal memory cell array 210. That is, since four redundancy word lines RWL are provided in FIG. 2, four defective memory cells that may occur in the normal memory cell array 210 can be replaced with four redundancy memory cells.
The dummy word lines DWL of the dummy memory cell array 230 are connected to the ground terminal VSS and, as mentioned above, no data access operation is performed on the dummy memory cell array 230.
Meanwhile, semiconductor memory devices has been manufactured for low power and high integration. Hence, voltages applied to semiconductor memory devices get lower, and capacitances of memory cells get smaller. As a result, memory cell characteristics related to a sensing margin or refresh are degraded. Those limitations may be solved by designing the memory cell having a large capacitance. However, this approach is not suitable because such a design will increase the size of the semiconductor memory device.